OpenASIPToolset for designing and programming customized instruction-set processors and generating processor RTL.
Toolset for designing and programming customized instruction-set processors and generating processor RTL.
OpenASIP helps engineers design and program customized processors and programmable accelerators. Its co-design flow connects high-level programs to synthesizable VHDL or Verilog processor descriptions and instruction-parallel binaries. Developers can customize register files, function units, operations and datapath connections. The toolset runs on Unix-style systems such as Linux, with Transport Triggered Architecture as its default programming model.
OpenASIP README · Reviewed 2026-11-03
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Repository created
2015-10-22
Repository push
2026-10-28
2015-10-22GitHub release
2026-03-13 · v2.2Repository push
2026-10-28
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GitHub release
Published 2026-03-13
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